Functional verification methodology for microprocessors using the Genesys test-program generator

Developing an architecture validation suite: application to the PowerPC architecture

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Validating the intel pentium 4 microprocessor

Proceedings of the 38th annual Design Automation Conference

Hole analysis for functional coverage data

Proceedings of the 39th annual Design Automation Conference

Solving the generalized mask constraint for test generation of binary floating point add operation

Theoretical Computer Science - Real numbers and computers

Validating the Intel® Pentium® 4 Microprocessor

DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)

Coverage directed test generation for functional verification using bayesian networks

Proceedings of the 40th annual Design Automation Conference

Generating random solutions for constraint satisfaction problems

Eighteenth national conference on Artificial intelligence

A BNF-based automatic test program generator for compatible microprocessor verification

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Functional Coverage Metric Generation from Temporal Event Relation Graph

Proceedings of the conference on Design, automation and test in Europe - Volume 1

Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification

IEEE Design & Test

Defining coverage views to improve functional coverage analysis

Proceedings of the 41st annual Design Automation Conference

An automatic testbench generation tool for a SystemC functional verification methodology

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design

A generic micro-architectural test plan approach for microprocessor verification

Proceedings of the 42nd annual Design Automation Conference

FPgen - a test generation framework for datapath floating-point verification

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Piparazzi: a test program generator for micro-architecture flow verification

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Enhancing the control and efficiency of the covering process [logic verification]

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation

IEEE Transactions on Computers

Advanced Analysis Techniques for Cross-Product Coverage

IEEE Transactions on Computers

Decimal floating-point in z9: an implementation and testing perspective

IBM Journal of Research and Development

Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions

Proceedings of the conference on Design, automation and test in Europe

Using a constraint satisfaction formulation and solution techniques for random test program generation

IBM Systems Journal

Pseudorandom verification and emulation of an MPEG-2 transport demultiplexor

IBM Journal of Research and Development

Using virtual coverage to hit hard-to-reach events

HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing

Checking architectural outputs instruction-by-instruction on acceleration platforms

Proceedings of the 49th Annual Design Automation Conference

Injecting floating-point testing knowledge into test generators

HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing