The design and verification of the AlphaStation 600 5-series workstation
Digital Technical Journal - Special 10th anniversary issue
Digital Technical Journal - Special 10th anniversary issue
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Integrating the MPEG-2 subsystem for digital television
IBM Journal of Research and Development
Design of an MPEG-2 transport demultiplexor core
IBM Journal of Research and Development
Design of an MPEG-2 transport demultiplexor core
IBM Journal of Research and Development
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This paper describes two complementary approaches to performance verification for an MPEG-2 transport demultiplexor. The performance of such devices is difficult to verify during the design phase because of the many independent bus interfaces to which they may be connected and the numerous operating configurations that may be required. To address these problems, we have devised both a pseudorandom verification "environment," employing "controlled random" simulation, and a hardware-emulation platform based on field-programmable gate arrays (FPGAs). Actual hardware verification has shown the effectiveness of using these two methods together, and the overall approach can be applied to other design programs.