AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Number-Theoretic Test Generation for Directed Rounding
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Generation and Analysis of Hard to Round Cases for Binary Floating Point Division
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
FPgen - a test generation framework for datapath floating-point verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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Floating-point unit (FPU) verification is a known challenge, due to the variety of corner cases both in its data path and control flow. We have identified a gap in the coverage of FP corner cases that combine special data and control scenarios. We propose a solution based on combining the deep FP knowledge of a special FP test generator with the strength of a general-purpose test generator. We present a novel FP testing knowledge package (FPTK) that consists of a weighted set of FP scenarios. We explain the flow of combining the existing tools with the FPTK and demonstrate its effect.