Crafting a compiler
Compiler design in C
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
User defined coverage—a tool supported methodology for design verification
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Verification Techniques for a MIPS Compatibvle Embedded Control Processor
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
Improving Test Quality Through Resource Reallocation
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Automaton: An Autonomous Coverage-Based Multiprocessor System Verification Environment
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Design Verification of a Super-Scalar RISC Processor
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Generating concurrent test-programs with collisions for multi-processor verification
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Adaptive test program generation: planning for the unplanned
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
X-Gen: a random test-case generator for systems and SoCs
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Automatic functional test program generation for microprocessor verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
WWW business applications based on the cellular model
Journal of Computer Science and Technology
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A novel Backus-Naur-form- (BNF-) based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented in this paper. We use X86 architecture to illustrate our design method. Our method is equally applicable to other processor architectures by redefining BNF production rules. Design issues for an automatic program generator (APG) are first outlined. We have resolved the design issues and implemented the APG by a top-down recursive descent parsing method which was originated from compiler design. Our APG can produce not only random test programs but also a sequence of instructions for a specific module to be tested by specifying a user menu-driven file. In addition, test programs generated by our APG have the features of no infinite loop, not entering illegal states, controllable data dependency, flexible program size, and data cache testable. Our method has been shown to be efficient and feasible for the development of an APG compared with other approaches. We have also developed a coverage tool to integrate with the APG. Experimental evaluation of the generated test programs indicates that our APG, with the guidance of the coverage tool, only needs to generate a small number of test programs to sustain high coverage.