Innovative verification strategy reduces design cycle time for high-end SPARC processor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hardware emulation for functional verification of K5
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A C-based RTL design verification methodology for complex microprocessor
DAC '97 Proceedings of the 34th annual Design Automation Conference
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Verification of a microprocessor using real world applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems
IBM Journal of Research and Development - POWER5 and packaging
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
IBM Journal of Research and Development
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EDA in IBM: past, present, and future
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the International Conference on Computer-Aided Design
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Simulation-based verification is an integral part of a modern microprocessor's design effort. Commonly, several checking techniques are deployed alongside the simulator to detect and localize each functional bug manifestation. Among these, a widespread technique entails comparing a microprocessor design's outputs with a golden model at the architectural granularity, instruction-by-instruction. However, due to exponential growth in design complexity, the performance of software-based simulation falls far short of achieving an acceptable level of coverage, which typically requires billions of simulation cycles. Hence, verification engineers rely on simulation acceleration platforms. Unfortunately, the intrinsic characteristics of these platforms make the adoption of the checking solutions mentioned above a challenging goal: for instance, the lockstep execution of a software checker together with the design's simulation is no longer feasible. To address this challenge we propose an innovative solution for instruction-by-instruction (IBI) checking tailored to acceleration platforms. We provide novel design techniques to decouple event tracing from checking by including specialized tracing logic and by adding a post-simulation checking phase. Note that simulation performance in acceleration platforms degrades when increasing the number of signals that are traced; hence, it is imperative to generate a compact summary of the information required for checking, collecting and tracing only a few bits of information per cycle.