Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Opportunities and challenges for better than worst-case design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Fractal Coherence: Scalably Verifiable Cache Coherence
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Validating a modern microprocessor
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Hi-index | 0.00 |
Abstract: Developing a new leading-edge IA-32 microprocessor is an immensely complicated undertaking, and it should come as no surprise to learn that logic bugs exist in the design. This is particularly true when, as is the case with the Pentium®4 processor, the microarchitecture is significantly more complex than any previous IA-32 microprocessor and the implementation borrowed almost nothing from any previous implementation. The purpose of this paper is to provide data on the bugs that were found prior to initial silicon on the Pentium®4 processor, and to describe how we went about the task of finding them. We hope that by sharing our experience and insights, other microprocessor designers and validators will be able to benefit from them. As Doug Clark [1] has remarked: "Finding a bug should be a cause for celebration. Each discovery is a small victory; each marks an incremental improvement in the design."