High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
An axiomatic basis for computer programming
Communications of the ACM
Automatically validating temporal safety properties of interfaces
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
Partitioned model checking from software specifications
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Embedded tutorial: formal equivalence checking between system-level models and RTL
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Validating High-Level Synthesis
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Formal Verification for High-Assurance Behavioral Synthesis
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
An industrially effective environment for formal hardware verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalence checking for behaviorally synthesized pipelines
Proceedings of the 49th Annual Design Automation Conference
Handling design and implementation optimizations in equivalence checking for behavioral synthesis
Proceedings of the 50th Annual Design Automation Conference
Microprocessors & Microsystems
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Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checking of RTL generated through behavioral synthesis. The optimizations exploit the high-level structure of the ESL description to ameliorate verification complexity. Experiments on representative benchmarks indicate that the optimizations can handle equivalence checking of synthesized designs with tens of thousands of lines of RTL.