Validating High-Level Synthesis

Authors:
Sudipta Kundu;Sorin Lerner;Rajesh Gupta
Affiliations:
University of California, San Diego CA 92093-0404;University of California, San Diego CA 92093-0404;University of California, San Diego CA 92093-0404
Venue:
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Year:
2008

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Abstract

The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the process of generating Register Transfer Level (RTL) design from these initial high-level programs. Unfortunately, this translation process itself can be buggy, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. In this paper, we present an approach to validate the result of HLS against the initial high-level program using insights from translation validation, automated theorem proving and relational approaches to reasoning about programs. We have implemented our validating technique and have applied it to a highly parallelizing HLS framework called SPARK. We present the details of our algorithm and experimental results.