Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
RTL c-based methodology for designing and verifying a multi-threaded processor
Proceedings of the 39th annual Design Automation Conference
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Introduction to Generalized Symbolic Trajectory Evaluation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
High level validation of next-generation microprocessors
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
An equivalence checking methodology for hardware oriented C-based specifications
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Hardware verification using ANSI-C programs as a reference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Transition-by-transition FSM traversal for reachability analysis in bounded model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Decomposing image computation for symbolic reachability analysis using control flow information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Tunneling and slicing: towards scalable BMC
Proceedings of the 45th annual Design Automation Conference
Formal Verification for High-Assurance Behavioral Synthesis
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Optimizing equivalence checking for behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
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With the trends toward higher-level design, verification models written in software, and hardware/software codesign, it is increasingly important to verify that RTL hardware behaves correctly according to an executable software specification. In this paper, we propose a natural way to formalize a cycle-accurate software specification as an annotated control flow graph, and then we introduce a novel partitioned model-checking algorithm that exploits the annotated control flow graph. Preliminary experimental results show that our new method runs faster than standard model checking.