High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Code Generation for Functional Validation of Pipelined Microprocessors
Journal of Electronic Testing: Theory and Applications
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Tightly integrate dynamic verification with formal verification: a GSTE based approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Partitioned model checking from software specifications
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
An enhanced framework for microprocessor test-program generation
EuroGP'03 Proceedings of the 6th European conference on Genetic programming
Integration of CP and compilation techniques for instruction sequence test generation
CPAIOR'08 Proceedings of the 5th international conference on Integration of AI and OR techniques in constraint programming for combinatorial optimization problems
Simulation vs. formal: absorb what is useful; reject what is useless
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Maximal models of assertion graph in GSTE
TAMC'06 Proceedings of the Third international conference on Theory and Applications of Models of Computation
Validating a modern microprocessor
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Deterministic dynamic monitors for linear-time assertions
FATES'06/RV'06 Proceedings of the First combined international conference on Formal Approaches to Software Testing and Runtime Verification
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Moore's Law continues to drive an inexorable increase in the number of transistors that can be integrated onto a single die. Computer architects continue to find ways to use all of these transistors to design ever more complex microprocessors. At the same time, competitive pressures are dictating shorter design cycles and faster time to market, while design team size has reached (and perhaps exceeded) the limit beyond which further growth is impracticable. This paper outlines some of the approaches being considered to address the challenge of validating Intel's next-generation IA32 microarchitecture. Building on the lessons learned from validating the Pentium/spl reg/ 4 processor, it addresses the role of a higher-level abstraction (above the current RTL model) and a broader application of formal verification techniques to the validation problem.