Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Prioritized Traversal: Efficient Reachability Analysis for Verification and Falsification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
High level validation of next-generation microprocessors
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
A Formal Verification Methodology for Checking Data Integrity
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Developing critical systems with PLD components
Proceedings of the 10th international workshop on Formal methods for industrial critical systems
Tightly integrate dynamic verification with formal verification: a GSTE based approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Partitioned model checking from software specifications
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Use of C/C++ models for architecture exploration and verification of DSPs
Proceedings of the 43rd annual Design Automation Conference
Verification through the principle of least astonishment
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Pre-RTL formal verification: an intel experience
Proceedings of the 45th annual Design Automation Conference
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
on the design of a formal debugger for system architecture
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Tool Building Requirements for an API to First-Order Solvers
Electronic Notes in Theoretical Computer Science (ENTCS)
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
3-valued circuit SAT for STE with automatic refinement
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Explaining symbolic trajectory evaluation by giving it a faithful semantics
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
SAT-based assistance in abstraction refinement for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Automatic refinement and vacuity detection for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Validating a modern microprocessor
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Formal verification of pentium ® 4 components with symbolic simulation and inductive invariants
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
A new SAT-based algorithm for symbolic trajectory evaluation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
NeVer: a tool for artificial neural networks verification
Annals of Mathematics and Artificial Intelligence
A case for runtime validation of hardware
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Formal methods for ranking counterexamples through assumption mining
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Formal property verification has been an effective complement to pre-silicon validation of several Intel Pentium 4 CPU designs at Intel Corporation. The principal objective of this program has been to prove design correctness rather than hunt for bugs. In the process, we have evolved our tools and methodology and are now applying FPV techniques to protocol level properties. Moving forward, new technologies such as GSTE and SAT offer the potential to significantly increase the scope of what can be formally verified. This paper will discuss the application of FPV to validation of the Intel Pentium 4 microarchitecture and some approaches being considered to broaden the application of FV techniques, particularly at a higher level of design abstraction.