Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
Dynamically Discovering Likely Program Invariants to Support Program Evolution
IEEE Transactions on Software Engineering - Special issue on 1999 international conference on software engineering
Validating the intel pentium 4 microprocessor
Proceedings of the 38th annual Design Automation Conference
POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Tracking down software bugs using automatic anomaly detection
Proceedings of the 24th International Conference on Software Engineering
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Improving simulation-based verification by means of formal methods
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
IODINE: a tool to automatically infer dynamic invariants for hardware designs
Proceedings of the 42nd annual Design Automation Conference
Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Automatic generation of complex properties for hardware designs
Proceedings of the conference on Design, automation and test in Europe
Inferno: streamlining verification with inferred semantics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scalable specification mining for verification and diagnosis
Proceedings of the 47th Design Automation Conference
GoldMine: automatic assertion generation using data mining and static analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Formal verification of pentium ® 4 components with symbolic simulation and inductive invariants
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
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Bug-fixing in deeply embedded portions of the logic is typically accompanied by the post-facto addition to new assertions which cover the bug scenario. Formally verifying properties defined over such deeply embedded portions of the logic is challenging because formal methods do not scale to the size of the entire logic, and verifying the property on the embedded logic in isolation typically throws up a large number of counterexamples, many of which are spurious because the scenarios they depict are not possible in the entire logic. In this paper we introduce the notion of ranking the counterexamples so that only the most likely counterexamples are presented to the designer. Our ranking is based on assume properties mined from simulation traces of the entire logic. We define a metric to compute a belief for each assume property that is mined, and rank counterexamples based on their conflicts with the mined assume properties. Experimental results demonstrate an amazing correlation between the real counterexamples (if they exist) and the proposed ranking metric, thereby establishing the proposed method as a very promising verification approach.