Tracking down software bugs using automatic anomaly detection
Proceedings of the 24th International Conference on Software Engineering
Efficient incremental algorithms for dynamic detection of likely invariants
Proceedings of the 12th ACM SIGSOFT twelfth international symposium on Foundations of software engineering
IODINE: a tool to automatically infer dynamic invariants for hardware designs
Proceedings of the 42nd annual Design Automation Conference
Verification through the principle of least astonishment
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Inferno: streamlining verification with inferred semantics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scalable specification mining for verification and diagnosis
Proceedings of the 47th Design Automation Conference
GoldMine: automatic assertion generation using data mining and static analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Property analysis and design understanding
Proceedings of the Conference on Design, Automation and Test in Europe
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Word level feature discovery to enhance quality of assertion mining
Proceedings of the International Conference on Computer-Aided Design
Formal methods for ranking counterexamples through assumption mining
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Automatic generation of compact formal properties for effective error detection
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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Property checking is a promising approach to prove the correctness of today's complex designs. However, in practice this requires the formulation of formal properties which is a time consuming and non-trivial task. Therefore the acceptance and efficiency of formal verification techniques can be raised by an automated support for formulating design properties. In this paper we propose a new methodology to automatically generate complex properties for a given design. The tool, Dianosis, implements this methodology by analyzing a simulation trace. The extracted properties describe the abstract design behavior and are presented in a format that is easy to read and can be added to the set of properties used for formal or assertion-based verification. We provide experimental results on industrial hardware designs that show the effectiveness of Dianosis and motivate the practical use.