Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Model checking
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Vacuity Detection in Temporal Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Efficient Detection of Vacuity in ACTL Formulas
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints
Journal of Automated Reasoning
A Coverage Analysis for Safety Property Lists
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Exploiting Resolution Proofs to Speed Up LTL Vacuity Detection for BMC
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Easier and More Informative Vacuity Checks
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Automatic generation of complex properties for hardware designs
Proceedings of the conference on Design, automation and test in Europe
Temporal Logic Query Checking: A Tool for Model Exploration
IEEE Transactions on Software Engineering
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
MTV '08 Proceedings of the 2008 Ninth International Workshop on Microprocessor Test and Verification
Analyzing Functional Coverage in Bounded Model Checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Formalization and validation of a subset of the European Train Control System
Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering - Volume 2
An abstraction-refinement framework for trigger querying
SAS'11 Proceedings of the 18th international conference on Static analysis
Validation of requirements for hybrid systems: A formal approach
ACM Transactions on Software Engineering and Methodology (TOSEM)
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Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are several techniques that can check if a set of formal properties forms a complete specification of a design. But, in contrast to simulation-based methods, like random testing, formal verification requires a detailed knowledge of the design implementation. Finding the correct set of properties is a tedious and time consuming process. In this paper, two techniques are presented that provide automatic support for writing properties in a quality-driven BMC flow. The first technique can be used to analyze properties in order to remove redundant assumptions and to separate different scenarios. The second technique - inverse property checking - automatically generates valid properties for a given expected behavior. The techniques are integrated with a coverage check for BMC. Using the presented techniques, the number of iterations to obtain full coverage can be reduced, saving time and effort.