Focusing processor policies via critical-path prediction
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Bugs as deviant behavior: a general approach to inferring errors in systems code
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Trace analysis of Erlang programs
ACM SIGPLAN Notices
Powerful Techniques for the Automatic Generation of Invariants
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Debugging temporal specifications with concept analysis
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
A Sense of Self for Unix Processes
SP '96 Proceedings of the 1996 IEEE Symposium on Security and Privacy
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Improving simulation-based verification by means of formal methods
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Automatically Inferring Temporal Properties for Program Evolution
ISSRE '04 Proceedings of the 15th International Symposium on Software Reliability Engineering
IODINE: a tool to automatically infer dynamic invariants for hardware designs
Proceedings of the 42nd annual Design Automation Conference
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Automatic generation and inference of interface properties from program source code
Companion to the 21st ACM SIGPLAN symposium on Object-oriented programming systems, languages, and applications
Verification through the principle of least astonishment
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Automatic generation of complex properties for hardware designs
Proceedings of the conference on Design, automation and test in Europe
Learnability of probabilistic automata via oracles
ALT'05 Proceedings of the 16th international conference on Algorithmic Learning Theory
Orchestrated multi-level information flow analysis to understand SoCs
Proceedings of the 48th Design Automation Conference
Automated feature localization for hardware designs using coverage metrics
Proceedings of the 49th Annual Design Automation Conference
Bridging pre- and post-silicon debugging with BiPeD
Proceedings of the International Conference on Computer-Aided Design
Formal methods for ranking counterexamples through assumption mining
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Understanding designers' intentions and accurately verifying a design are major obstacles for verification engineers today. Currently available debugging tools, such as waveform viewers, are unwieldy, often requiring the user to search through millions of cycles of logic simulation data to locate a problem. In this paper, we present Inferno, a novel solution capable of automatically extracting semantic information from a design's interface from simulation information. The semantic structure of an interface's communication protocol is presented to the user as a set of transactions, that is, monolithic communication units that have typically been observed several times during the logic simulation. Transactions can graphically be presented to the user and used as an aid to understand and validate the communication protocol of a design's interface. In addition, approved transactions can also be encoded as assertions expressed in a hardware description language (HDL) and used in constrained-random simulation to certify that the interface protocol adheres to the set of observed (and user-approved) transactions. Moreover, we developed a new closed-loop verification methodology based on Inferno, called transactional verification, which leverages approved transactions to describe correct design behavior. In our methodology, transactions are concurrently extracted during a constraint-based random simulation: the anomalous ones are flagged as potentially buggy and presented to the user for inspection. In the experimental results, we evaluate the performance and the quality of the results of Inferno on a broad range of testbench designs and several of their interfaces, including a number of communication intellectual properties and the OpenSPARC T1 8-core processor from Sun.