POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
IODINE: a tool to automatically infer dynamic invariants for hardware designs
Proceedings of the 42nd annual Design Automation Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Engineering trust with semantic guardians
Proceedings of the conference on Design, automation and test in Europe
MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
The Daikon system for dynamic detection of likely invariants
Science of Computer Programming
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Automated Debug of Speed Path Failures Using Functional Tests
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Inferno: streamlining verification with inferred semantics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BLoG: post-silicon bug localization in processors using bug localization graphs
Proceedings of the 47th Design Automation Conference
Scalable specification mining for verification and diagnosis
Proceedings of the 47th Design Automation Conference
Transaction based pre-to-post silicon validation
Proceedings of the 48th Design Automation Conference
MACE: model-inference-assisted concolic exploration for protocol and vulnerability discovery
SEC'11 Proceedings of the 20th USENIX conference on Security
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The growing complexity of modern chips has caused an increasing share of the verification effort to shift towards post-silicon validation. This phase is challenged by poor observability, limited off-chip bandwidth, and complex, concurrent communication interfaces. Furthermore, pre-silicon verification and post-silicon validation methodologies are very different and share little information between them. As as result, the diagnosis and debugging of post-silicon failures is very much an ad-hoc and time-consuming task that is largely unable to leverage the vast body of design knowledge available in pre-silicon. We propose BiPeD, a novel methodology to identify the exact time and location of post-silicon bugs. During pre-silicon verification, BiPeD learns the correct behavior of a design's communication patterns. In post-silicon, this knowledge is used to detect errors by means of a reconfigurable hardware unit. When an error is detected, bug reproduction is not necessary: a diagnosis software algorithm analyzes information stored in the hardware unit to provide a wide range of debugging information. We show that our system provides accurate bug localization for a range of failures on the industrial-size OpenSPARC T2 design.