Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
ML for the working programmer (2nd ed.)
ML for the working programmer (2nd ed.)
Automatic generation of invariants and intermediate assertions
Theoretical Computer Science - Special issue: principles and practice of constraint programming
Automatic generation of state invariants from requirements specifications
SIGSOFT '98/FSE-6 Proceedings of the 6th ACM SIGSOFT international symposium on Foundations of software engineering
Automatic Generation of Invariants
Formal Methods in System Design - Special issue on The First Federated Logic Conference (FLOC'96), part II
Model checking
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Technique for Invariant Generation
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
InVeST: A Tool for the Verification of Invariants
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
Combinational equivalence checking through function transformation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
An Enhanced Cut-points Algorithm in Formal Equivalence Verification
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Compositional model checking of software product lines using variation point obligations
Automated Software Engineering
Formal methods for ranking counterexamples through assumption mining
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We describe a practical methodology for large-scale formal verification of control-intensive industrial circuits. It combines symbolic simulation with human-generated inductive invariants, and a proof tool for verifying implications between constraint lists. The approach has emerged from extensive experiences in the formal verification of key parts of the Intel IA-32 Pentium ® 4 microprocessor designs. We discuss it the context of two case studies: Pentium 4 register renaming mechanism and BUS recycle logic.