High capacity and automatic functional extraction tool for industrial VLSI circuit designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Formal verification of pentium ® 4 components with symbolic simulation and inductive invariants
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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BDD-based cut-points verification is widely used in formal verification. The authors have recently developed a cut-points verification algorithm that is unique in that it avoids generation of false-negatives and allows simplification of the circuits to be compared based on reconvergence of input variables. Here we describe several refinements and enhancements that lead both to drastic speedup as well increase in capacity. These methods are already implemented in Intel's combinational verifier CLEVER and show very promissing results on real life examples from the pentium design family.