Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Abstraction by Symbolic Indexing Transformations
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
The Mathematical Foundation fo Symbolic Trajectory Evaluation
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
A new SAT-based algorithm for symbolic trajectory evaluation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A novel formalization of symbolic trajectory evaluation semantics in Isabelle/HOL
Theoretical Computer Science
SAT-based assistance in abstraction refinement for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
An introduction to symbolic trajectory evaluation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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Symbolic Trajectory Evaluation (STE) is a formal verification technique for hardware. The current STE semantics is not faithful to the proving power of existing STE tools, which obscures the STE theory unnecessarily. In this paper, we present a new closure semantics for STE which does match the proving power of STE model-checkers, and makes STE easier to understand.