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Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Scalable hybrid verification of complex microprocessors
Proceedings of the 38th annual Design Automation Conference
Compositional Reasoning in Model Checking
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Assertion-Based Design
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Proceedings of the conference on Design, automation and test in Europe - Volume 1
Opportunities and challenges for better than worst-case design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Complementary use of runtime validation and model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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Increasing hardware design complexity has resulted in significant challenges for hardware design verification. The growing “verification gap” between the complexity of what we can verify and what we can fabricate/design is indicative of a crisis that is likely to get only worse with increasing complexity. A variety of methodology and tool solutions have been proposed to deal with this crisis, but there is little optimism that a single solution or even a set of cooperative solutions will be scalable to enable future design verification to be cost effective. It is time we reconcile ourselves to the fact that hardware, like software, will be shipped with bugs in it. One possible solution to deal with this inevitable scenario is to provide support for runtime validation that detects functional failures at runtime and then recovers from such failures. Such runtime validation hardware will increasingly be used to handle dynamic operational failures caused by reduced reliability of devices due to large process variations as well as increasing soft errors. Expanding the use of such hardware to deal with functional design failures provides for an on-chip insurance policy when design errors inevitably slip through the verification process. This paper will discuss the strengths and weaknesses of this form of design validation, some possible forms this may take, and implications on design methodology.