High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Verification strategy for integration 3G baseband SoC
Proceedings of the 40th annual Design Automation Conference
Formal verification: is it real enough?
Proceedings of the 42nd annual Design Automation Conference
Principles of Sequential-Equivalence Verification
IEEE Design & Test
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural trade-offs that must be made for a practical implementation. The same models can be reused during the verification of the RTL subsequently developed, provided that various "hooks" which are desirable during the verification process are considered while creating these high level models. In addition, consideration must be given to the qualitative content of these high level models to permit an optimal verification flow allowing for compromise between features of the model and the completeness of the verification. Thus, high quality design and verification are achieved by the use of valid models and the valid use of models. In this paper, we describe our approach and show examples from a typical image processing application.