Design and validation of computer protocols
Design and validation of computer protocols
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SAFECOMP '00 Proceedings of the 19th International Conference on Computer Safety, Reliability and Security
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ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
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This paper describes an industrial application in formal verification. The analyzed system is the Safety Logic of an interlocking system for the control of railway stations developed by Ansaldo. The Safety Logic is a process-based software architecture, which can be configured to implement different functions and control stations of different topology. The applied technique, model checking, allows for the representation of the analyzed system as a finite state machines. Specialized algorithms allow for the automatic and efficient verification of requirements by means of an exhaustive exploration of the state space. In this paper we describe how a formal model of the Safety Logic has been develped in the language of the spin model checker. This model retains the configurability features of the Safety Logic. Furthermore, we discuss how the automated verification of several significant process configurations was carried out without incurring into the state explosion problem.