Distributed LTL model-checking in SPIN
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
Parallel state space construction for model-checking
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
Local Parallel Model Checking for the Alternation-Free µ-Calculus
Proceedings of the 9th International SPIN Workshop on Model Checking of Software
Parallel Shared-Memory State-Space Exploration in Stochastic Modeling
IRREGULAR '97 Proceedings of the 4th International Symposium on Solving Irregularly Structured Problems in Parallel
Scalable Distributed On-the-Fly Symbolic Model Checking
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Parallel Model Checking for the Alternation Free µ-Calculus
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Extended Overhead Analysis for OpenMP (Research Note)
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Distributing Timed Model Checking - How the Search Order Matters
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Achieving Scalability in Parallel Reachability Analysis of Very Large Circuits
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Parallelizing the Murphi Verifier
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
A hierarchical classification of overheads in parallel programs
Proceedings of the First IFIP TC10 International Workshop on Software Engineering for Parallel and Distributed Systems
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
Distributed explicit fair cycle detection: set based approach
SPIN'03 Proceedings of the 10th international conference on Model checking software
Distributed Verification of Multi-threaded C++ Programs
Electronic Notes in Theoretical Computer Science (ENTCS)
Measuring and Evaluating Parallel State-Space Exploration Algorithms
Electronic Notes in Theoretical Computer Science (ENTCS)
A Multi-Core Solver for Parity Games
Electronic Notes in Theoretical Computer Science (ENTCS)
Scalable Multi-core Model Checking Fairness Enhanced Systems
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Tutorial: parallel model checking
Proceedings of the 14th international SPIN conference on Model checking software
Generating counter-examples through randomized guided search
Proceedings of the 14th international SPIN conference on Model checking software
Scalable multi-core LTL model-checking
Proceedings of the 14th international SPIN conference on Model checking software
Proceedings of the IEEE/ACM international conference on Automated software engineering
Distributed model-checking and counterexample search for CTL logic
International Journal of Critical Computer-Based Systems
Distributed CTL model-checking and counterexample search
VECoS'09 Proceedings of the Third international conference on Verification and Evaluation of Computer and Communication Systems
An experiment on parallel model checking of a CTL fragment
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
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In this article we present the parallelisation of an explicit-state CTL* model checking algorithm for a virtual shared-memory high-performance parallel machine architecture. The algorithm uses a combination of private and shared data structures for implicit and dynamic load balancing with minimal synchronisation overhead. The performance of the algorithm and the impact that different design decisions have on the performance are analysed using both mathematical cost models and experimental results. The analysis shows not only the practicality and effective speedup of the algorithm, but also the main pitfalls of parallelising model checking for shared-memory architectures.