Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The existence of refinement mappings
Theoretical Computer Science
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
CTL model checking based on forward state traversal
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Approximation and decomposition of binary decision diagrams
DAC '98 Proceedings of the 35th annual Design Automation Conference
Validation with guided search of the state space
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hybrid verification using saturated simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
On-the-Fly Model Checking of RCTL Formulas
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Structural Symmetry and Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Design Constraints in Symbolic Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Symmetry Reductions inModel Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
On Combining Formal and Informal Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Proving Correctness of Distributed Algorithms Using High-Level Petri Nets - A Case Study
CSD '98 Proceedings of the 1998 International Conference on Application of Concurrency to System Design
Efficient Fixpoint Computation for Invariant Checking
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Comparing Symbolic and Explicit Model Checking of a Software System
Proceedings of the 9th International SPIN Workshop on Model Checking of Software
Traversal Techniques for Concurrent Systems
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Techniques for Smaller Intermediary BDDs
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
An Algorithmic Approach to Design Exploration
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
Meta-BDDs: A Decomposed Representation for Layered Symbolic Manipulation of Boolean Functions
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Mixing Forward and Backward Traversals in Guided-Prioritized BDD-Based Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Survey on Directed Model Checking
Model Checking and Artificial Intelligence
Biased model checking using flows
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Automatic generation of hints for symbolic traversal
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A fine-grained fullness-guided chaining heuristic for symbolic reachability analysis
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
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Symbolic model checking is an increasingly popular debugging tool based on Binary Decision Diagrams (BDDs). The size of the diagrams, however, often prevents its application to large designs. The lack of flexibility of the conventional breadth-first approach to state search is often responsible for the excessive growth of the BDDs. In this paper we show that the use of hints to guide the exploration of the state space may result in orders-of-magnitude reductions in time and space requirements. We apply hints to invariant checking. The hints address the problems posed by difficult image computations, and are effective in both proving and refuting invariants. We show that good hints can often be found with the help of simple heuristics by someone who understands the circuit well enough to devise simulation stimuli or verification properties for it. We present an algorithm for guided traversal and discuss its efficient implementation.