Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Model checking, abstraction, and compositional verification
Model checking, abstraction, and compositional verification
New techniques for efficient verification with implicitly conjoined BDDs
DAC '94 Proceedings of the 31st annual Design Automation Conference
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
State minimization of finite state machines using implicit techniques
State minimization of finite state machines using implicit techniques
Techniques for efficient formal verification using binary decision diagrams
Techniques for efficient formal verification using binary decision diagrams
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Approximate reachability with BDDs using overlapping projections
DAC '98 Proceedings of the 35th annual Design Automation Conference
Improving symbolic traversals by means of activity profiles
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
On the Descriptive and Algorithmic Power of Parity Ordered Binary Decision Diagrams
STACS '97 Proceedings of the 14th Annual Symposium on Theoretical Aspects of Computer Science
Hints to accelerate Symbolic Traversal
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Partial-Order Reduction in Symbolic State Space Exploration
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Petri Net Analysis Using Boolean Manipulation
Proceedings of the 15th International Conference on Application and Theory of Petri Nets
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Automatic state space decomposition for approximate FSM traversal based on circuit analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for approximate FSM traversal based on state space decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Incremental and Modular Technique for Checking LTL\X Properties of Petri Nets
FORTE '07 Proceedings of the 27th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
MC-SOG: An LTL Model Checker Based on Symbolic Observation Graphs
PETRI NETS '08 Proceedings of the 29th international conference on Applications and Theory of Petri Nets
Hierarchical decision diagrams to exploit model structure
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
High-Level Petri Net Model Checking with AlPiNA
Fundamenta Informaticae - Applications and Theory of Petri Nets and Other Models of Concurrency, 2010
| Hi-index | 0.00 |
Binary decision diagrams (BDDs) have proven to be a powerful technique for combating the state explosion problem. Their application to verification is usually centered around the computation of the transitive closure of some binary relation. The closure is usually computed with a fixed point algorithm that expands some set until it stops growing. Unfortunately, the BDDs that arise during the computation are often much larger than the final BDD. The computation may thus fail because of lack of memory, even if the final BDD would be small. To alleviate this problem, this paper proposes four variations of the fixed point algorithm. They reduce the sizes of the intermediary BDDs by "rounding down" the sets they represent in such a way that the final BDD does not change. Consequently, more iterations may be required to compute the fixed point, but the intermediary BDDs computed during the run are smaller. The performance of the new algorithms is illustrated with a large number of experiments.