Approximate reachability with BDDs using overlapping projections
DAC '98 Proceedings of the 35th annual Design Automation Conference
Approximate reachability don't cares for CTL model checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Improved approximate reachability using auxiliary state variables
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
To split or to conjoin: the question in image computation
Proceedings of the 37th Annual Design Automation Conference
Least fixpoint approximations for reachability analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Counterexample-guided choice of projections in approximate symbolic model checking
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Techniques for Smaller Intermediary BDDs
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Transition-by-transition FSM traversal for reachability analysis in bounded model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Disjunctive image computation for embedded software verification
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Disjunctive image computation for software verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Property-driven partitioning for abstraction refinement
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Analyzing k-step induction to compute invariants for SAT-based property checking
Proceedings of the 47th Design Automation Conference
Sequential logic synthesis using symbolic bi-decomposition
Proceedings of the Conference on Design, Automation and Test in Europe
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Exploiting circuit structure is a key issue in the implementation of algorithms for state space decomposition when the target is approximate FSM traversal. Given the gate-level description of a sequential circuit, the information about its structure can be captured by evaluating the affinity between pairs or groups of latches. Two main factors have to be considered in carrying out the structural analysis of a sequential circuit: latch connectivity and latch correlation. The first one takes into account the mutual dependency of each memory element on the others; the second one tells us how related are the functions realized by the logic feeding each latch. In this paper we estimate the affinity of two latches by combining these two factors, and we use this measure to formulate the state space decomposition problem as a graph partitioning problem. We propose an algorithm to automatically determine “good” partitions of the latch set which induce state space decomposition, and we present approximate FSM traversal and logic optimization results for the largest ISCAS'89 sequential benchmarks