Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Approximate reachability with BDDs using overlapping projections
DAC '98 Proceedings of the 35th annual Design Automation Conference
Validation with guided search of the state space
DAC '98 Proceedings of the 35th annual Design Automation Conference
Verification by approximate forward and backward reachability
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
An Iterative Approach to Language Containment
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Automatic state space decomposition for approximate FSM traversal based on circuit analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Overapproximating Reachable Sets by Hamilton-Jacobi Projections
Journal of Scientific Computing
Effective heuristics for counterexample-guided abstraction refinement
Proceedings of the 17th ACM Great Lakes symposium on VLSI
GSTE is partitioned model checking
Formal Methods in System Design
Auxiliary state machines + context-triggered properties in verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Multiple-counterexample guided iterative abstraction refinement: an industrial evaluation
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Making abstraction-refinement efficient in model checking
COCOON'11 Proceedings of the 17th annual international conference on Computing and combinatorics
A probabilistic learning approach for counterexample guided abstraction refinement
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Searching for counter-examples adaptively
IWFM'03 Proceedings of the 6th international conference on Formal Methods
An efficient approach for abstraction-refinement in model checking
Theoretical Computer Science
Detecting spurious counterexamples efficiently in abstract model checking
Proceedings of the 2013 International Conference on Software Engineering
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BDD-based symbolic techniques of approximate reachability analysis based on decomposing the circuit into a collection of overlapping sub-machines (also referred to as overlapping projections) have been recently proposed. Computing a superset of the reachable states in this fashion is susceptible to false negatives. Searching for real counterexamples in such an approximate space is liable to failure. In this paper, the "hybridization effect" induced by the choice of projections is identified as the cause for the failure. A heuristic based on Hamming Distance is proposed to improve the choice of projections, that reduces the hybridization effect and facilitates either a genuine counterexample or proof of the property. The ideas are evaluated on a real large design example from the PCI Interface unit in the MAGIC chip of the Stanford FLASH Multiprocessor.