Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
An automata-theoretic approach to linear temporal logic
Proceedings of the VIII Banff Higher order workshop conference on Logics for concurrency : structure versus automata: structure versus automata
Tearing based automatic abstraction for CTL model checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Incremental CTL model checking using BDD subsetting
DAC '98 Proceedings of the 35th annual Design Automation Conference
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Formal Methods in System Design
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Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
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CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Stochastic Colored Petri Net Models for Rainbow Optical Networks
Application of Petri Nets to Communication Networks, Advances in Petri Nets
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Automatic Abstraction Techniques for Propositional µ-calculus Model Checking
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
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IEEE Transactions on Computers
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Proceedings of the conference on Design, automation and test in Europe - Volume 1
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Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
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ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Effective heuristics for counterexample-guided abstraction refinement
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Interpolant Learning and Reuse in SAT-Based Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Model checking with Boolean Satisfiability
Journal of Algorithms
Underapproximation for model-checking based on universal circuits
Information and Computation
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TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Underapproximation for model-checking based on random cryptographic constructions
CAV'07 Proceedings of the 19th international conference on Computer aided verification
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ACM Transactions on Computational Logic (TOCL)
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IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
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COCOON'11 Proceedings of the 17th annual international conference on Computing and combinatorics
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SAS'11 Proceedings of the 18th international conference on Static analysis
Minimizing counterexample with unit core extraction and incremental SAT
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Abstraction refinement for bounded model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Interleaved invariant checking with dynamic abstraction
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A probabilistic learning approach for counterexample guided abstraction refinement
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Abstraction refinement with craig interpolation and symbolic pushdown systems
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
An efficient approach for abstraction-refinement in model checking
Theoretical Computer Science
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ICFEM'12 Proceedings of the 14th international conference on Formal Engineering Methods: formal methods and software engineering
Detecting spurious counterexamples efficiently in abstract model checking
Proceedings of the 2013 International Conference on Software Engineering
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In this paper, we describe a completely automated framework for iterative abstraction refinement that is fully integrated into a formal-verification environment. This environment consists of three basic software tools: Forecast, a BDD-based model checker, Thunder, a SAT-based bounded model checker, and MCE, a technology for multiple-counterexample analysis. In our framework, the initial abstraction is chosen relative to the property under verification. The abstraction is model checked by Forecast; in case of failure, a counter example is returned. Our framework includes an abstract counterexample analyzer module that applies techniques for bounded model checking to check whether the abstract counter example holds in the concrete model. If it does, it is extended to a concrete counter example. This important capability is provided as a separate tool that also addresses one of the major problems of verification by manual abstraction. If the counter example is spurious, we use a novel refinement heuristic based on MCE to guide the refinement. After the part of the abstract model to be refined is chosen, our refinement algorithm computes a new abstraction that includes as much logic as possible without adding too many new variables, therefore striking a balance between refining the abstraction and keeping its size manageable. We demonstrate the effectiveness of our framework on challenging Intel designs that were not amenable to BDD-based model-checking approaches.