Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Fate and Free Will in Error Traces
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SAT-based unbounded symbolic model checking
Proceedings of the 40th annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Multiple-counterexample guided iterative abstraction refinement: an industrial evaluation
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Computation of minimal counterexamples by using black box techniques and symbolic methods
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Synthesizing complementary circuits automatically
Proceedings of the 2009 International Conference on Computer-Aided Design
Finding unsatisfiable subformulas with stochastic method
IDEAL'07 Proceedings of the 8th international conference on Intelligent data engineering and automated learning
A heuristic local search algorithm for unsatisfiable cores extraction
ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part III
Synthesizing complementary circuits automatically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimizing models for tseitin-encoded SAT instances
SAT'13 Proceedings of the 16th international conference on Theory and Applications of Satisfiability Testing
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It is a hotly researching topic to eliminate irrelevant variables from counterexample, to make it easier to be understood. K Ravi proposes a two-stages counterexample minimization algorithm. This algorithm is the most effective one among all existing approaches, but time overhead of its second stage(called BFL) is very large due to one call to SAT solver per candidate variable to be eliminated. So we propose a faster counterexample minimization algorithm based on unit core extraction and incremental SAT. First, for every unsatisfiable instance of BFL, we perform unit core extraction algorithm to extract the set of variables that are sufficient to lead to conflict, all variables not belong to this set can be eliminated simultaneously. In this way, we can eliminate many variables with only one call to SAT solver. At the same time, we employ incremental SAT approach to share learned clauses between similar instances of BFL, to prevent overlapped state space from being searched repeatedly. Theoretic analysis and experiment result show that, our approach is 1 order of magnitude faster than K Ravi's algorithm, and still retains its ability to eliminate irrelevant variables.