“Sometimes” and “not never” revisited: on branching versus linear time temporal logic
Journal of the ACM (JACM) - The MIT Press scientific computation series
Tree automata, Mu-Calculus and determinacy
SFCS '91 Proceedings of the 32nd annual symposium on Foundations of computer science
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Model checking
Symbolic Model Checking
A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Vacuity Detection in Temporal Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Detecting Errors Before Reaching Them
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Efficient Detection of Vacuity in ACTL Formulas
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Alternating-time Temporal Logic
FOCS '97 Proceedings of the 38th Annual Symposium on Foundations of Computer Science
Reasoning about infinite computation paths
SFCS '83 Proceedings of the 24th Annual Symposium on Foundations of Computer Science
From symptom to cause: localizing errors in counterexample traces
POPL '03 Proceedings of the 30th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Explaining abstract counterexamples
Proceedings of the 12th ACM SIGSOFT twelfth international symposium on Foundations of software engineering
A Faster Counterexample Minimization Algorithm Based on Refutation Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Algorithms for compacting error traces
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A fast counterexample minimization approach with refutation analysis and incremental SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Simulation-based bug trace minimization with BMC-based refinement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Disjunctive image computation for software verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Automated Approach for the Interpretation of Counter-Examples
Electronic Notes in Theoretical Computer Science (ENTCS)
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Explaining Counterexamples Using Causality
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Making the Most of BMC Counterexamples
Electronic Notes in Theoretical Computer Science (ENTCS)
What went wrong: explaining counterexamples
SPIN'03 Proceedings of the 10th international conference on Model checking software
Model checking-based genetic programming with an application to mutual exclusion
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Fault localization for data-centric programs
Proceedings of the 19th ACM SIGSOFT symposium and the 13th European conference on Foundations of software engineering
Minimizing counterexample with unit core extraction and incremental SAT
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
On the complexity of error explanation
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Explaining counterexamples using causality
Formal Methods in System Design
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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The ability to generate counterexamples for failing properties is often cited as one of the strengths of model checking. However, it is often difficult to interpret long error traces in which many variables appear. Further, a traditional error trace presents only one possible behavior of the system causing the failure, with no further annotation. Our objective is to "capture more of the error" in an error trace to make debugging easier.We present an enhanced error trace in an alternation of fated (forced) and free segments. The fated segments showunavoidable progress towards the error while the free segments show choices that, if avoided, may have prevented the error. This segmentation raises the questions of whether the fated segment should indeed be inevitable and whether the free segments are critical in causing the error. Addressing these questions may help the user analyze the error better.