Tool-supported program abstraction for finite-state verification
ICSE '01 Proceedings of the 23rd International Conference on Software Engineering
From symptom to cause: localizing errors in counterexample traces
POPL '03 Proceedings of the 30th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Finding Feasible Counter-examples when Model Checking Abstracted Java Programs
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Fate and Free Will in Error Traces
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Proceedings of the 17th IEEE international conference on Automated software engineering
Tool support for checking railway interlocking designs
SCS '05 Proceedings of the 10th Australian workshop on Safety critical systems and software - Volume 55
What went wrong: explaining counterexamples
SPIN'03 Proceedings of the 10th international conference on Model checking software
Model-Based Generation of Interlocking Controller Software from Control Tables
ECMDA-FA '08 Proceedings of the 4th European conference on Model Driven Architecture: Foundations and Applications
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Model checking is an automatic technique used for the verification of finite systems. A model checker explores the full state space of a given model and checks it against a set of requirements. If a state exists in which a requirement is not satisfied most tools will generate a counter-example. Counter-examples are useful for debugging a model and determining if an error exists in the modelled system. However, they can be difficult for end users to understand and this may limit the take-up of model checking in industry. This paper describes a domain-specific approach to automatically interpreting counter-examples and presenting the results in an intuitive form to the end user. Our research extends previous work on model checking railway signalling control tables with signalling engineers from Queensland Rail.