Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Handbook of theoretical computer science (vol. B)
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Chaff: engineering an efficient SAT solver
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SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
Model Checking of Safety Properties
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Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
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Static Property Checking Using ATPG v.s. BDD Techniques
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Iterative Abstraction using SAT-based BMC with Proof Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Abstraction refinement for bounded model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
An analysis of SAT-based model checking techniques in an industrial environment
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Improvements to the implementation of interpolant-based model checking
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Efficient abstraction refinement in interpolation-based unbounded model checking
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
The localization reduction and counterexample-guided abstraction refinement
Time for verification
A single-instance incremental SAT formulation of proof- and counterexample-based abstraction
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
VMCAI'12 Proceedings of the 13th international conference on Verification, Model Checking, and Abstract Interpretation
Minimum satisfying assignments for SMT
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Automatic abstraction in SMT-Based unbounded software model checking
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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Unbounded model checking methods based on Boolean satisfiability (SAT) solvers are proving to be a viable alternative to BDD-based model checking. These methods include, for example, interpolation based and sequential ATPG-based approaches. In this paper, we explore the implications of using abstraction refinement in conjunction with interpolation-based model checking. Based on experiments using a large industrial benchmark set, we conclude that when using interpolation-based model checking, measures must be taken to prevent the overhead of abstraction refinement from dominating runtime. We present two new approaches to this problem. One is a hybrid approach that decides heuristically when to apply abstraction. The other is a very coarse but inexpensive abstraction method based on ideas from ATPG. This approach can produce order-of-magnitude reductions in memory usage, allowing significantly larger designs to be verified.