Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
Conflict driven learning in a quantified Boolean Satisfiability solver
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Can SAT be used to Improve Sequential ATPG Methods?
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
An Efficient Sequential SAT Solver With Improved Search Strategies
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Simulation-based bug trace minimization with BMC-based refinement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Bounded model checking with QBF
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
sKizzo: a suite to evaluate and certify QBFs
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
An analysis of SAT-based model checking techniques in an industrial environment
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Binary clause reasoning in QBF
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Consistency checking of all different constraints over bit-vectors within a SAT solver
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Spatial and temporal design debug using partial MaxSAT
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Beyond CNF: A Circuit-Based QBF Solver
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
The day Sherlock Holmes decided to do EDA
Proceedings of the 46th Annual Design Automation Conference
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nenofex: expanding NNF for QBF solving
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
Leveraging dominators for preprocessing QBF
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pipelined microprocessors optimization and debugging
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Exploiting circuit representations in QBF solving
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
A uniform approach for generating proofs and strategies for both true and false QBF formulas
IJCAI'11 Proceedings of the Twenty-Second international joint conference on Artificial Intelligence - Volume Volume One
Automated design debugging in a testbench-based verification environment
Microprocessors & Microsystems
Bridging the gap between dual propagation and CNF-based QBF solving
Proceedings of the Conference on Design, Automation and Test in Europe
Microprocessors & Microsystems
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Many CAD for VLSI techniques use time-frame expansion, also known as the Iterative Logic Array representation, to model the sequential behavior of a system. Replicating industrial-size designs for many time-frames may impose impractically excessive memory requirements. This work proposes a performance-driven, succinct and parametrizable Quantified Boolean Formula (QBF) satisfiability encoding and its hardware implementation for modeling sequential circuit behavior. This encoding is then applied to three notable CAD problems, namely Bounded Model Checking (BMC), sequential test generation and design debugging. Extensive experiments on industrial circuits confirm outstanding run-time and memory gains compared to state-of-the-art techniques, promoting the use of QBF in CAD for VLSI.