Model checking
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Fading Algorithm For Sequential Fault Diagnosis
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Simulation-based bug trace minimization with BMC-based refinement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Improved Design Debugging Using Maximum Satisfiability
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Algorithms for maximum satisfiability using unsatisfiable cores
Proceedings of the conference on Design, automation and test in Europe
Towards more effective unsatisfiability-based maximum satisfiability algorithms
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
On finding all minimally unsatisfiable subformulas
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
On solving the partial MAX-SAT problem
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cause clue clauses: error localization using maximum satisfiability
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Post-silicon fault localisation using maximum satisfiability and backbones
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coverage-based trace signal selection for fault localisation in post-silicon validation
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying possible error sources in the design. Unfortunately, these techniques do not provide any information regarding the time at which the bug is active during an error trace or counter-example. This work introduces an automated debug technique that provides the user with both spatial and temporal information about the source of error. The proposed method is based on a Partial MaxSAT formulation which models errors at the CNF clause level instead of the traditional gate or module level. Thus, error sites are identified based on erroneous implications that correspond to locations both in the design and in the error trace. Experiments demonstrate that we can provide this additional information at no extra cost in run time and are able to prune about 61% of all simulation time frames from the debugging process. When compared to a trivial formulation we observe a performance improvement of up to two orders of magnitude and 5× on average when using the proposed formulation.