A theory of diagnosis from first principles
Artificial Intelligence
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
Efficient Design Error Correction of Digital Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
AMUSE: a minimally-unsatisfiable subformula extractor
Proceedings of the 41st annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Fading Algorithm For Sequential Fault Diagnosis
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
MUP: a minimal unsatisfiability prover
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-the-fly resolve trace minimization
Proceedings of the 44th annual Design Automation Conference
Fixing Design Errors with Counterexamples and Resynthesis
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints
Journal of Automated Reasoning
Improved Design Debugging Using Maximum Satisfiability
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Spatial and temporal design debug using partial MaxSAT
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Explaining Counterexamples Using Causality
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Generalizing Core-Guided Max-SAT
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From RTL to silicon: the case for automated debug
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Managing complexity in design debugging with sequential abstraction and refinement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Computing small unsatisfiable cores in satisfiability modulo theories
Journal of Artificial Intelligence Research
Post-silicon fault localisation using maximum satisfiability and backbones
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Explaining counterexamples using causality
Formal Methods in System Design
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coverage-based trace signal selection for fault localisation in post-silicon validation
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported quite well using simulation or formal verification. But locating the fault site is typically a time consuming manual task. Techniques to automate debugging and diagnosis have been proposed. Approaches based on Boolean Satisfiability (SAT) have been demonstrated to be very effective. In this work debugging on the gate level is considered. Unsatisfiable cores contained in a SAT instance for debugging are used (1) to determine all suspects, and (2) to speed-up the debugging process. In comparison to standard SAT-based debugging, the experimental results show a significant speed-up for debugging multiple faults.