Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Model checking
A machine program for theorem-proving
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Assertion-Based Design
Testing of Digital Systems
Searching for truth: techniques for satisfiability of boolean formulas
Searching for truth: techniques for satisfiability of boolean formulas
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Simulation-based bug trace minimization with BMC-based refinement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Improved Design Debugging Using Maximum Satisfiability
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Assertion-Based Verification: Industry Myths to Realities (Invited Tutorial)
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Scalable don't-care-based logic optimization and resynthesis
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
A formal approach for debugging arithmetic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Solver technology for system-level to RTL equivalence checking
Proceedings of the Conference on Design, Automation and Test in Europe
Managing verification error traces with bounded model debugging
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic Fault Localization for Property Checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From RTL to silicon: the case for automated debug
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Post-silicon bug diagnosis with inconsistent executions
Proceedings of the International Conference on Computer-Aided Design
Path directed abstraction and refinement in SAT-based design debugging
Proceedings of the 49th Annual Design Automation Conference
Coverage-based trace signal selection for fault localisation in post-silicon validation
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Design debugging is a major bottleneck in modern very large scale integration design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical design blocks exceeding half a million synthesized logic gates and error traces in the thousands of clock cycles, the complexity of the debugging problem poses a great challenge to automated debugging techniques. This paper aims to address this daunting challenge by introducing the bounded model debugging methodology that iteratively analyzes bounded sequences of the error trace. Two techniques are introduced in this methodology to solve this growing problem. The first technique iteratively analyzes bounded subsequences of the error trace of increasing size until the error is found or the entire trace is analyzed. The second technique partitions the error trace into non-overlapping bounded sequences of clock cycles which are each separately analyzed. A discussion of these two techniques is presented and a unified methodology that leverages the strengths of both techniques is developed. Empirical results on real industrial designs show that for large designs and long error traces the proposed methodology can find the actual error in 79% of cases with the first technique and 100% of cases with the second technique. In cases where the methodology is not used only 21% of cases are able to find the actual error. These numbers confirm the benefits of the proposed methodology to allow conventional automated debuggers to handle much larger real-life circuits.