An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging
Proceedings of the 32nd annual international symposium on Computer Architecture
Cooperative bug isolation
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
A New Post-Silicon Debug Approach Based on Suspect Window
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Automated Debug of Speed Path Failures Using Functional Tests
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BLoG: post-silicon bug localization in processors using bug localization graphs
Proceedings of the 47th Design Automation Conference
Scalable specification mining for verification and diagnosis
Proceedings of the 47th Design Automation Conference
Automated data analysis solutions to silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Threadmill: a post-silicon exerciser for multi-threaded processors
Proceedings of the 48th Design Automation Conference
Machine learning-based anomaly detection for post-silicon bug diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Space sensitive cache dumping for post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
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The complexity of modern chips intensifies verification challenges, and an increasing share of this verification effort is shouldered by post-silicon validation. Focusing on the first silicon prototypes, post-silicon validation poses critical new challenges such as intermittent failures, where multiple executions of a same test do not yield a consistent outcome. These are often due to on-chip asynchronous events and electrical effects, leading to extremely time-consuming, if not unachievable, bug diagnosis and debugging processes. In this work, we propose a methodology called BPS (Bug Positioning System) to support the automatic diagnosis of these difficult bugs. During post-silicon validation, lightweight BPS hardware logs a compact encoding of observed signal activity over multiple executions of the same test: some passing, some failing. Leveraging a novel post-analysis algorithm, BPS uses the logged activity to diagnose the bug, identifying the approximate manifestation time and critical design signals. We found experimentally that BPS can localize most bugs down to the exact root signal and within about 1,000 clock cycles of their occurrence.