GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Embedded tutorial: formal equivalence checking between system-level models and RTL
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Constructing efficient formal models from high-level descriptions using symbolic simulation
International Journal of Parallel Programming
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Memory modeling in ESL-RTL equivalence checking
Proceedings of the 44th annual Design Automation Conference
A lightweight component caching scheme for satisfiability solvers
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
A decision procedure for bit-vectors and arrays
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Effective preprocessing in SAT through variable and clause elimination
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System verification of concurrent RTL modules by compositional path predicate abstraction
Proceedings of the 49th Annual Design Automation Conference
Handling design and implementation optimizations in equivalence checking for behavioral synthesis
Proceedings of the 50th Annual Design Automation Conference
Microprocessors & Microsystems
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Checking the equivalence of a system-level model against an RTL design is a major challenge. The reason is that usually the system-level model is written by a system architect, whereas the RTL implementation is created by a hardware designer. This approach leads to two models that are significantly different. Checking the equivalence of real-life designs requires strong solver technology. The challenges can only be overcome with a combination of bit-level and word-level reasoning techniques, combined with the right orchestration. In this paper, we discuss solver technology that has shown to be effective on many real-life equivalence checking problems.