Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Calysto: scalable and precise extended static checking
Proceedings of the 30th international conference on Software engineering
Construction of concrete verification models from C++
Proceedings of the 45th annual Design Automation Conference
Efficient symbolic simulation of low level software
Proceedings of the conference on Design, automation and test in Europe
Solver technology for system-level to RTL equivalence checking
Proceedings of the Conference on Design, Automation and Test in Europe
Modular bug detection with inertial refinement
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Compositional CLP-based test data generation for imperative languages
LOPSTR'10 Proceedings of the 20th international conference on Logic-based program synthesis and transformation
Formal deadlock checking on high-level SystemC designs
Proceedings of the International Conference on Computer-Aided Design
Alternate and learn: finding witnesses without looking all over
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Automating hardware design at higher levels of abstraction requires first and foremost a formal model of the high-level specification. This formal model is the basis of many EDA applications such as synthesis, analysis or verification. It should have a compact form, but still be close to the original description. In this paper, we propose using a Data-Flow-Graph (DFG) as a formal model. We present a new approach for generating a DFG from a high-level C++ specification based on symbolic simulation. The main advantage of using symbolic simulation for this task is that conceptually all C++ constructs can be handled. No restriction to a subset of constructs is required. Furthermore, our approach focuses on the quality of the resulting DFG. It attempts to minimize the number of nodes while still producing DFGs that adhere to the original specification.