Efficient self-learning techniques for SAT-based test generation

Authors:
Ang Li;Mingsong Chen
Affiliations:
East China Normal University, Shanghai, China;East China Normal University, Shanghai, China
Venue:
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Year:
2012

Citing 16
Cited 0

Model checking

Model checking
A machine program for theorem-proving

Communications of the ACM
Chaff: engineering an efficient SAT solver

Proceedings of the 38th annual Design Automation Conference
The Impact of Branching Heuristics in Propositional Satisfiability Algorithms

EPIA '99 Proceedings of the 9th Portuguese Conference on Artificial Intelligence: Progress in Artificial Intelligence
Pruning Techniques for the SAT-Based Bounded Model Checking Problem

CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Tuning SAT Checkers for Bounded Model Checking

CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Coverage directed test generation for functional verification using bayesian networks

Proceedings of the 40th annual Design Automation Conference
Refining the SAT decision ordering for bounded model checking

Proceedings of the 41st annual Design Automation Conference
A Circuit SAT Solver With Signal Correlation Guided Learning

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Incremental deductive & inductive reasoning for SAT-based bounded model checking

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
UML Activity Diagram-Based Automatic Test Case Generation For Java Programs

The Computer Journal
Functional test generation using efficient property clustering and learning techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Property Learning Techniques for Efficient Generation of Directed Tests

IEEE Transactions on Computers
An analysis of SAT-based model checking techniques in an industrial environment

CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
System-Level Validation: High-Level Modeling and Directed Test Generation Techniques

System-Level Validation: High-Level Modeling and Directed Test Generation Techniques

Quantified Score

Hi-index	0.00

Visualization

Abstract

SAT-based approaches are promising for automated generation of directed tests. However, due to the state space explosion problem, these methods do not scale well for complex designs. Although various heuristics are proposed to address test generation complexity, most of them require expert knowledge regarding the detailed structure and behavior information of designs explicitly, which limits their usage. This paper proposes promising techniques to derive profitable learnings from the SAT instance itself. The obtained self-learnings can efficiently reduce the chance of long distance backtracks and improve satisfying assignment convergence rate during the SAT search. Experimental results demonstrate that our method can reduce the test generation time by several orders of magnitude.