GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A fast pseudo-boolean constraint solver
Proceedings of the 40th annual Design Automation Conference
Testing of Digital Systems
Managing Don't Cares in Boolean Satisfiability
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate Diagnosis of Multiple Faults
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Generation of shorter sequences for high resolution error diagnosis using sequential SAT
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On the relation between simulation-based and SAT-based diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Model-Based Debugging -- State of the Art And Future Challenges
Electronic Notes in Theoretical Computer Science (ENTCS)
Automated Fault Localization for C Programs
Electronic Notes in Theoretical Computer Science (ENTCS)
Estimating functional coverage in bounded model checking
Proceedings of the conference on Design, automation and test in Europe
A succinct memory model for automated design debugging
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Pervasive diagnosis: the integration of diagnostic goals into production plans
AAAI'08 Proceedings of the 23rd national conference on Artificial intelligence - Volume 3
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans - Special issue on model-based diagnostics
Increasing the accuracy of SAT-based debugging
Proceedings of the Conference on Design, Automation and Test in Europe
Facilitating unreachable code diagnosis and debugging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Journal of Computer and System Sciences
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Automated design debugging in a testbench-based verification environment
Microprocessors & Microsystems
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Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean satisfiability. This formulation takes advantage of modern Boolean satisfiability solvers that handle large circuits in a computationally efficient manner. An extensive suite of experiments with large sequential circuits confirm the robustness and efficiency of the proposed approach. The results further suggest that Boolean satisfiability provides an effective platform for sequential logic debugging.