Quantum computation and quantum information
Quantum computation and quantum information
A reversible carry-look-ahead adder using control gates
Integration, the VLSI Journal
Proceedings of the 7th Colloquium on Automata, Languages and Programming
A transformation based algorithm for reversible logic synthesis
Proceedings of the 40th annual Design Automation Conference
A Family of Logical Fault Models for Reversible Circuits
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Checking equivalence of quantum circuits and states
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
An XQDD-Based Verification Method for Quantum Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Equivalence Checking of Reversible Circuits
ISMVL '09 Proceedings of the 2009 39th International Symposium on Multiple-Valued Logic
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Logical reversibility of computation
IBM Journal of Research and Development
Efficient Simulation-Based Debugging of Reversible Logic
ISMVL '10 Proceedings of the 2010 40th IEEE International Symposium on Multiple-Valued Logic
Proceedings of the Conference on Design, Automation and Test in Europe
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising direction so that several methods for synthesis, verification, and testing of reversible circuits have already been proposed. However, also methods for debugging, i.e., to determine error candidates in case of a failed verification, are required to complete the design flow. Even if first approaches have already been proposed, debugging of reversible circuits still is in the beginning. In this paper, we present an alternative method to automatically debug reversible circuits. We thereby focus on missing control errors -- an established error model in the design of reversible circuits. A new notion of an error candidate is proposed that relies on the observation of a necessary condition for error locations in reversible circuits. Using this notion, a set of error candidates is obtained that differs from the error candidates returned by previous methods. Thus, combining the approaches enhances the overall debugging flow. Experimental results demonstrate that a higher accuracy is obtained in significantly shorter run-time.