Enhancing debugging of multiple missing control errors in reversible logic
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Reducing the number of lines in reversible circuits
Proceedings of the 47th Design Automation Conference
Integration, the VLSI Journal
Realizing reversible circuits using a new class of quantum gates
Proceedings of the 49th Annual Design Automation Conference
RevKit: an open source toolkit for the design of reversible circuits
RC'11 Proceedings of the Third international conference on Reversible Computation
Transforming MCT circuits to NCVW circuits
RC'11 Proceedings of the Third international conference on Reversible Computation
Reversible circuits: recent accomplishments and future challenges for an emerging technology
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Synthesis and optimization of reversible circuits—a survey
ACM Computing Surveys (CSUR)
On the "Q" in QMDDs: efficient representation of quantum functionality in the QMDD data-structure
RC'13 Proceedings of the 5th international conference on Reversible Computation
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Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits' primary inputs and outputs must be in pure logic states but the circuits may include elementary quantum gates in addition to reversible logic gates. The specification can include don't-cares arising from constant inputs, garbage outputs, and total or partial don't-cares in the underlying target function. The paper explores well-known techniques from irreversible equivalence checking and how they can be applied in the domain of reversible circuits. Two approaches are considered. The first employs decision diagram techniques and the second uses Boolean satisfiability. Experimental results show that for both methods, circuits with up to 27,000 gates, as well as adders with more than 100 inputs and outputs, are handled in under three minutes with reasonable memory requirements.