Quantum computation and quantum information
Quantum computation and quantum information
A reversible carry-look-ahead adder using control gates
Integration, the VLSI Journal
Proceedings of the 7th Colloquium on Automata, Languages and Programming
A transformation based algorithm for reversible logic synthesis
Proceedings of the 40th annual Design Automation Conference
Test Generation and Fault Localization for Quantum Circuits
ISMVL '05 Proceedings of the 35th International Symposium on Multiple-Valued Logic
A Family of Logical Fault Models for Reversible Circuits
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Gate-level simulation of quantum circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Checking equivalence of quantum circuits and states
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An XQDD-Based Verification Method for Quantum Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Equivalence Checking of Reversible Circuits
ISMVL '09 Proceedings of the 2009 39th International Symposium on Multiple-Valued Logic
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
Exact multiple-control toffoli network synthesis with SAT techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Logical reversibility of computation
IBM Journal of Research and Development
Reducing Reversible Circuit Cost by Adding Lines
ISMVL '10 Proceedings of the 2010 40th IEEE International Symposium on Multiple-Valued Logic
Proceedings of the Conference on Design, Automation and Test in Europe
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault testing for reversible circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reversible cascades with minimal garbage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Algorithm for Synthesis of Reversible Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RevKit: an open source toolkit for the design of reversible circuits
RC'11 Proceedings of the Third international conference on Reversible Computation
Reversible circuits: recent accomplishments and future challenges for an emerging technology
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Synthesis and optimization of reversible circuits—a survey
ACM Computing Surveys (CSUR)
Design of efficient reversible logic-based binary and BCD adder circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Trading off circuit lines and gate costs in the synthesis of reversible logic
Integration, the VLSI Journal
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Reversible logic became a promising alternative to traditional circuits because of its applications e.g. in low-power design and quantum computation. As a result, design of reversible circuits attracted great attention in the last years. The number of circuit lines is thereby a major criterion since it e.g. affects the still limited resource of qubits. Nevertheless, all approaches introduced so far for synthesis of complex reversible circuits need a significant amount of additional circuit lines -- sometimes orders of magnitude more than the primary inputs. In this paper, we propose a post-process optimization method that addresses this problem. The general idea is to merge garbage output lines with appropriate constant input lines. To this end, parts of the circuits are re-synthesized. Experimental results show that by applying the proposed approach, the number of circuit lines can be reduced by 17% on average - in the best case by more than 40%. At the same time, the increase in the number of gates and the quantum costs, respectively, can be kept small.