A fast quantum mechanical algorithm for database search
STOC '96 Proceedings of the twenty-eighth annual ACM symposium on Theory of computing
Quantum computation and quantum information
Quantum computation and quantum information
A reversible carry-look-ahead adder using control gates
Integration, the VLSI Journal
Proceedings of the 7th Colloquium on Automata, Languages and Programming
A transformation based algorithm for reversible logic synthesis
Proceedings of the 40th annual Design Automation Conference
A new heuristic algorithm for reversible logic synthesis
Proceedings of the 41st annual Design Automation Conference
Techniques for the synthesis of reversible Toffoli networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
Optimized reversible binary-coded decimal adders
Journal of Systems Architecture: the EUROMICRO Journal
Algorithms for quantum computation: discrete logarithms and factoring
SFCS '94 Proceedings of the 35th Annual Symposium on Foundations of Computer Science
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
Exact multiple-control toffoli network synthesis with SAT techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Logical reversibility of computation
IBM Journal of Research and Development
Reducing Reversible Circuit Cost by Adding Lines
ISMVL '10 Proceedings of the 2010 40th IEEE International Symposium on Multiple-Valued Logic
ESOP-Based Toffoli Network Generation with Transformations
ISMVL '10 Proceedings of the 2010 40th IEEE International Symposium on Multiple-Valued Logic
Reducing the number of lines in reversible circuits
Proceedings of the 47th Design Automation Conference
Reversible circuit synthesis using a cycle-based approach
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates
ISMVL '11 Proceedings of the 2011 41st IEEE International Symposium on Multiple-Valued Logic
Realizing reversible circuits using a new class of quantum gates
Proceedings of the 49th Annual Design Automation Conference
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reversible cascades with minimal garbage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Algorithm for Synthesis of Reversible Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Depth-optimized reversible circuit synthesis
Quantum Information Processing
Automatic design of low-power encoders using reversible circuit synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Motivated by its application in several emerging technologies, the synthesis of reversible circuits has received significant attention in the last decade. The proposed methods can roughly be divided into two different categories: (A) approaches ensuring the minimal number of circuit lines and (B) hierarchical approaches. Both synthesis paradigms have significant differences with respect to the gate costs and the number of lines in the resulting circuits. Hence, designers often have to deal with unsatisfactory results were either the gate costs or the number of circuit lines is disproportionately large. In this paper, the relation between the gate costs of a reversible circuit and the number of circuit lines is considered. We observe that by slightly increasing the number of circuit lines, significant reductions in the gate cost can be obtained. Vice versa, by accepting a small increase in the gate costs, the number of lines can significantly be reduced. Following these observations, two optimization approaches are applied to demonstrate and experimentally evaluate these effects. The optimization approaches generate alternative circuit realizations from which the best one can be picked with regard to the designers' requirements. As a result, a synthesis scheme is proposed that does not focus on a single cost metric, but trades off the competing requirements.