A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantum computation and quantum information
Quantum computation and quantum information
Proceedings of the 7th Colloquium on Automata, Languages and Programming
A transformation based algorithm for reversible logic synthesis
Proceedings of the 40th annual Design Automation Conference
Techniques for the synthesis of reversible Toffoli networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
Exact multiple-control toffoli network synthesis with SAT techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performability/energy tradeoff in error-control schemes for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust edge encoding technique for energy-efficient multi-cycle interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Algorithm for Synthesis of Reversible Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Reversible circuit synthesis of symmetric functions using a simple regular structure
RC'13 Proceedings of the 5th international conference on Reversible Computation
Exploiting negative control lines in the optimization of reversible circuits
RC'13 Proceedings of the 5th international conference on Reversible Computation
Trading off circuit lines and gate costs in the synthesis of reversible logic
Integration, the VLSI Journal
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The application of coding strategies is an established methodology to improve the characteristics of on-chip interconnect architectures. Therefore, design methods are required which realize the corresponding encoders and decoders with as small as possible overhead in terms of power and delay. In the past, conventional design methods have been applied for this purpose. This work proposes an entirely new direction which exploits design methods for reversible circuits. Here, much progress has been made in the last years. The resulting reversible circuits represent one-to-one mappings which can inherently work as logical descriptions for the desired encoders and decoders. Both, an exact and a heuristic synthesis approach, are introduced which rely on reversible design principles but also incorporate objectives from on-chip interconnect architectures. Experiments show that significant improvements with respect to power consumption, area, and delay can be achieved using the proposed direction.