A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
A machine program for theorem-proving
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
Quantum computation and quantum information
Quantum computation and quantum information
Proceedings of the 7th Colloquium on Automata, Languages and Programming
Reversible logic circuit synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A transformation based algorithm for reversible logic synthesis
Proceedings of the 40th annual Design Automation Conference
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Quantum Circuit Simplification Using Templates
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Fast synthesis of exact minimal reversible circuits using group theory
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Exact sat-based toffoli network synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Fast exact Toffoli network synthesis of reversible logic
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel synthesis algorithm for reversible circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reversible cascades with minimal garbage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Toffoli network synthesis with templates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Algorithm for Synthesis of Reversible Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
A library-based synthesis methodology for reversible logic
Microelectronics Journal
Reducing the number of lines in reversible circuits
Proceedings of the 47th Design Automation Conference
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Integration, the VLSI Journal
RevKit: an open source toolkit for the design of reversible circuits
RC'11 Proceedings of the Third international conference on Reversible Computation
Synthesis and optimization of reversible circuits—a survey
ACM Computing Surveys (CSUR)
BDD-Based Synthesis of Reversible Logic
International Journal of Applied Metaheuristic Computing
Design of efficient reversible logic-based binary and BCD adder circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Automatic design of low-power encoders using reversible circuit synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Reversible circuit synthesis of symmetric functions using a simple regular structure
RC'13 Proceedings of the 5th international conference on Reversible Computation
Exploiting negative control lines in the optimization of reversible circuits
RC'13 Proceedings of the 5th international conference on Reversible Computation
RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Trading off circuit lines and gate costs in the synthesis of reversible logic
Integration, the VLSI Journal
Upper bounds for reversible circuits based on Young subgroups
Information Processing Letters
| Hi-index | 0.03 |
Synthesis of reversible logic has become a very important research area in recent years. Applications can be found in the domain of low-power design, optical computing, and quantum computing. In the past, several approaches have been introduced that synthesize reversible networks with respect to a given function. Most of these methods only approximate a minimal network representation. In this paper, exact algorithms for the synthesis of multiple-control Toffoli networks are presented, i.e., algorithms that guarantee to find a network with the minimal number of gates. Our iterative algorithms formulate the synthesis problem as a sequence of decision problems. The decision problems are encoded as Boolean satisfiability (SAT) or SAT modulo theory (SMT) instances, respectively. As soon as one of these instances becomes satisfiable, a Toffoli network representation for the given function has been found. We show that choosing the encoding for synthesis is crucial for the resulting runtimes. Furthermore, we discuss the principal limits of the SAT and SMT approaches. To overcome these limits, we propose a method using problem-specific knowledge during synthesis. In addition, better embeddings to make irreversible functions reversible are considered. For the resulting synthesis problems, an improvement is presented that reduces the overall runtime by automatically setting the constant inputs to their optimal values. Experimental results on a large set of benchmarks demonstrate the differences between three exact synthesis algorithms. In addition, a comparison with the best-known heuristic results is provided. In summary, the results show that, for some benchmarks, the heuristic approaches have already found the minimal network, while for other benchmarks, significantly smaller networks exist.