Reversible computing: from mathematical group theory to electronical circuit experiment
Proceedings of the 2nd conference on Computing frontiers
Design of a compact reversible binary coded decimal adder circuit
Journal of Systems Architecture: the EUROMICRO Journal
Exact sat-based toffoli network synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Six Synthesis Methods for Reversible Logic
Open Systems & Information Dynamics
Reversible circuit technology mapping from non-reversible specifications
Proceedings of the conference on Design, automation and test in Europe
Techniques for the synthesis of reversible Toffoli networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reversible logic synthesis with Fredkin and Peres gates
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Optimized reversible binary-coded decimal adders
Journal of Systems Architecture: the EUROMICRO Journal
Quantified synthesis of reversible logic
Proceedings of the conference on Design, automation and test in Europe
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
Exact multiple-control toffoli network synthesis with SAT techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of a reversible PLD architecture
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Reducing the number of lines in reversible circuits
Proceedings of the 47th Design Automation Conference
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology
Microelectronics Journal
Ultra-area-efficient reversible multiplier
Microelectronics Journal
An efficient approach for designing and minimizing reversible programmable logic arrays
Proceedings of the great lakes symposium on VLSI
Reversible circuits: recent accomplishments and future challenges for an emerging technology
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Synthesis and optimization of reversible circuits—a survey
ACM Computing Surveys (CSUR)
BDD-Based Synthesis of Reversible Logic
International Journal of Applied Metaheuristic Computing
Design of efficient reversible logic-based binary and BCD adder circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Trading off circuit lines and gate costs in the synthesis of reversible logic
Integration, the VLSI Journal
Upper bounds for reversible circuits based on Young subgroups
Information Processing Letters
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The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. We start with the analysis of the number of garbage outputs that must be added to a multiple output function to make it reversible. We give a precise formula for the theoretical minimum of the required number of garbage outputs. For some benchmark functions, we calculate the garbage required by some proposed reversible design methods and compare it to the theoretical minimum. Based on the information about minimal garbage, we suggest a new reversible design method that uses the minimum number of garbage outputs. We show that any Boolean function can be realized as a reversible network in terms of this new approach by giving the theoretical method of finding such a network. Using a heuristics synthesis approach, we create a program and run it to compare results of our synthesis to the previously reported synthesis results for the benchmark functions with up to ten variables. Finally, we show that the synthesis for the proposed model can be accomplished with lower cost than the synthesis of EXOR programmable logic arrays.