An efficient approach for designing and minimizing reversible programmable logic arrays

Authors:
Sajib Kumar Mitra;Lafifa Jamal;Mineo Kaneko;Hafiz Md. Hasan Babu
Affiliations:
Samsung Bangladesh R&D Center Limited, Dhaka, Bangladesh;University of Dhaka, Dhaka, Bangladesh;Japan Advanced Institute of Sci. and Tech., Ishikawa, Japan;University of Dhaka, Dhaka, Bangladesh
Venue:
Proceedings of the great lakes symposium on VLSI
Year:
2012

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Abstract

Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3x3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbages and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbages, quantum costs and delay.