An efficient approach for designing and minimizing reversible programmable logic arrays
Proceedings of the great lakes symposium on VLSI
Compact DSOP and Partial DSOP Forms
Theory of Computing Systems
Upper bounds for reversible circuits based on Young subgroups
Information Processing Letters
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Minimization of AND-EXOR programmable logic arrays (PLAs) with input decoders corresponds to minimization of the number of products in Exclusive-OR sum-of-products expressions (ESOPs) for multiple-valued-input two-valued-output functions. A simplification algorithm for ESOPs that iteratively reduces the number of the products in ESOPs and then reduces the number of the literals is presented. Various rules are used to replace a pair of products with another one. Many AND-EXOR PLAs for arithmetic circuits have been simplified. In most cases, AND-EXOR PLAs required fewer products than AND-OR PLAs